Low complexity slicer architectures for N-tap look-ahead decision feedback equalizer (DFE) circuit implementations
AssigneeHuawei Technologies Co., Ltd.
InventorHuong Ho
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Abstract
A slicer circuit for use in a N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) wherein the slicer comprises overflow adders and sign adders, the slicer circuit including a first processing path for generating, based on a signal sample y(n), a most significant bit (MSB) for each of 2S*N possible output symbols of the DFE, the first processing path including (2S*N)/2 overflow adder circuits, and a second processing path for generating, based on the signal sample y(n), a least significant bit (LSB) for each of the 2S*N possible output symbols, the second processing path including 2S*N sign adder circuits.
Claims20
A slicer circuit for use in a N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) circuit configured to receive a signal sample y(n) and generate a corresponding estimated output symbol x(n),
- the slicer circuit comprising:
- a first processing path for generating, based on the signal sample y(n), a most significant bit (MSB) for each of 2S*N possible output symbols of the DFE circuit, the first processing path including (2S*N)/2 overflow adder circuits;
- and
- a second processing path for generating, based on the signal sample y(n), a least significant bit (LSB) for each of the 2S*N possible output symbols, the second processing path including 2S*N sign adder circuits, wherein N is the number of taps in the DFE circuit and S is the number of bits in the estimated output symbol x(n).
A method for slicing a received signal sample y(n) to generate a plurality of possible output symbols in an N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) circuit, comprising;
- generating, using (2S*N)/2 overflow adder circuits and based on the received signal sample y(n), a most significant bit (MSB) for each of 2S*N possible output symbols of the DFE circuit;
- and
- generating, using 2S*N sign adder circuits and based on the received signal sample y(n), a least significant bit (LSB) for each of the 2S*N possible output symbols, wherein N is the number of taps in the DFE circuit and S is the number of bits in an output symbol of the DFE circuit.
An N-tap, S-bit look-ahead decision feedback equalizer (DFE) circuit configured to receive a signal sample y(n) and generate a corresponding estimated output symbol x(n), the DFE circuit comprising:
- a slicer circuit configured to generate possible output symbols of the DFE based on the signal sample y(n), a slicer threshold T and N tap coefficients C1 . . . CN, the slicer circuit including:
- a first processing path for generating, based on the signal sample y(n), slicer threshold T and tap coefficients C1 . . . CN, a most significant bit (MSB) for each of the possible output symbols of the DFE circuit, the first processing path including ½(2S*N) overflow adder circuits, and
- a second processing path for generating, based on the signal sample y(n), slicer threshold T and tap coefficients C1 . . . CN, a least significant bit (LSB) for each of the possible output symbols of the DFE circuit, the second processing path including 2S*N sign adder circuits;
- and
- a multiplexer configured to, based on a previously estimated output signal, selectively output the estimated output symbol x(n) from among the possible output symbols generated by the slicer circuit, wherein N is the number of taps in the DFE circuit and S is the number of bits in the estimated output symbol x(n).
Dependencies are inferred from the claim text.