System, method and software program for tuneable equalizer adaptation using sample interpolation
AssigneeGlobalfoundries Inc.
InventorsTroy J. Beukema, Matthew B. Baecher
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AssigneeGlobalfoundries Inc.
InventorsTroy J. Beukema, Matthew B. Baecher
Estimating the term…
Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.
A system, comprising:
A method, comprising:
A non-transitory computer-readable storage device having stored thereon computer-readable instructions that, when executed by a computer, implement:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Operating in the time domain: adaptive, i.e. capable of adjustment during data reception
Analogue/digital conversion; Digital/analogue conversion: analogue/digital converters
Correction of synchronization errors: correction by interpolation
Adaptive, i.e. capable of adjustment during data reception: with a recursive structure
About 9 years 7 months of term left · ends 25 May 2036 (estimated)
In a conventional digital receiver system which samples data at a given BAUD rate (once per symbol transmission interval), there is no intermediate-time information available to adapt an analog continuous-time equalizer (“CTE”) and/or feed-forward equalizer (“FFE”) according to an optimal zero-force edge (“ZFE”) convergence (or lock) criterion.
Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation. Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to the ZFE convergence (or lock) criterion.
T. Toifl et. al. (“Low Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components”, IEEE Trans. Commun. vol. 54, no. 9, September 2006 pp. 1554-57) describes the basic concept of zero-forcing of jitter components by adapting a feed-forward equalizer.
The drawings are provided for illustrative purpose only and do not necessarily represent practical examples of the present invention to scale.
FIG. 1 shows a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention.
FIG. 2A shows a graph of an example fractional delay interpolator frequency response according to an embodiment of the present invention and FIG. 2B shows a corresponding example sixth order fractional delay interpolation polynomials used for the graph of FIG. 2A.
One embodiment of the present invention relates to a system for tuneable equalizer adaptation using sample interpolation. Another embodiment of the present invention relates to a method for tuneable equalizer adaptation using sample interpolation. Another embodiment of the present invention relates to a software program for tuneable equalizer adaptation using sample interpolation.
Various embodiments of the present invention are based upon the observation that the zero-forcing of jitter components is equivalent to decorrelating ISI that arises from a data bit and appears at an edge crossover position at, for example, 1.5 unit intervals (“UI”) delayed (from the data bit).
In various embodiments, the intermediate sample position data at the 1.5 unit interval delay is estimated using interpolation polynomials applied to the sampled data (i.e., the received data after analog-to-digital conversion). The sampled data is measured at discrete unit intervals with a time period “T” corresponding to an ADC sample rate of FS=1.0/T samples/sec.