US 9,853,807 B2 · Automatic detection of change in PLL locking trend

Abstract

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Claims20

Dependent claims

A phase lock loop (PLL) controller, comprising:

a clock generator configured to:
receive an error signal from a PLL, the error signal representing a difference between a frequency or a phase of a reference input signal of the PLL and a frequency or a phase of an output signal of the PLL, and
generate a clock signal based on the error signal;
a trend detector configured to:
sample the error signal in accordance with the clock signal, and
determine a trend of the sampled error signal;
and
a trend change detector configured to:
compare the trend of the sampled error signal to a previous trend of the sampled error signal to detect for a change in the trend of the sampled error signal, and
initiate a change in a mode of operation of the PLL upon detecting the change in the trend of the sampled error signal.

7 more elements

A method for operating a phase lock loop (PLL), the method comprising

receiving a first error signal from the PLL in a frequency tracking mode of operation, the first error signal representing a difference between a frequency of a reference input signal of the PLL and a frequency of an output signal of the PLL;
sampling the first error signal;
determining a trend of the sampled first error signal;
comparing the trend of the sampled first error signal to a previous trend of the sampled first error signal to detect for a change in the trend of the sampled first error signal;
initiating a change in a mode of operation of the PLL from the frequency tracking mode of operation to a phase tracking mode of operation upon detecting the change in the trend of the sampled first error signal;
and
receiving a second error signal from the PLL in the phase tracking mode of operation, the second error signal representing a difference between a phase of the reference input signal and a phase of the output signal.

4 more elements

Dependencies are inferred from the claim text.

Automatic detection of change in PLL locking trend

Life of this patent

Automatic detection of change in PLL locking trend

Life of this patent

Abstract

Claims20