Method and apparatus for conversion of value of analog signal to compressed digital word

A method for conversion of a value of an analog signal to a compressed digital word with a compression ratio not higher than a ratio of two natural numbers m and n using a conversion of the analog signal to a linear digital word according to a successive approximation scheme,

• wherein a number of bits of the linear digital word is not lower than m, and, at the same time, the number of bits of the linear digital word is higher than a number of bits of the compressed digital word, and the number of bits of the compressed digital word is not lower than n, and the compressed digital word comprises a group of v bits copied directly from the linear digital word, and a number of s bits that indicates a position of the group of v bits in the linear digital word, wherein v+s=n, and
• the bits of the linear digital word already evaluated by the use of a linear analog-to-digital converter are provided to a linear digital input of a compression module,
• wherein the conversion of a value of the analog signal to the linear digital word is terminated by the use of the compression module when all bits of a compression word have been evaluated,
• wherein a compression starts when the compression module detects an active state on a compression trigger input, and then a number equal to a difference between numbers m and v is written to a section number register in the compression module,
• wherein v is an arbitrarily chosen natural number smaller than n, and, after detection, on the basis of a bit ready signal, that a new output bit in the linear digital word has been evaluated by the linear analog-to-digital converter, a content of the section number register is decreased by one if a state of the new output bit in the linear digital word has been evaluated to zero,
• wherein the content of the section number register is not decreased if a state of the new output bit in the linear digital word has been evaluated to one, or if the content of the section number register has been already reduced to zero, and then, in both cases, the evaluation of next v bits of the linear digital word by the linear analog-to-digital converter is awaited, and a number of v occurrences of a bit ready signal is counted, and, afterwards, a complete conversion signal is generated by the compression module, which terminates the conversion of the analog signal to the linear digital word, and introduces the linear analog-to-digital converter to a standby state, and
• wherein the states of v bits of the linear digital word previously evaluated are assigned by the compression module, respectively, to Least Significant v Bits of the compressed word, and the content of the section number register is written by the compression module to Most Significant Bits of the compressed word.