Systems and methods of low power clocking for sleep mode radios
AssigneeTexas Instruments Incorporated
InventorsArun Paidimarri, Danielle Griffith, Alice Wang
Life of this patent
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Abstract
Systems and methods of low power docking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.
Claims25
A communications apparatus, comprising:
- a real time unit configured for tracking real time based on a first clock;
- application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
- a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock;
- a low-power low-accuracy oscillator (LPLAO) purposely mistuned by lowering a load capacitance of the LPLAO to be less than what is required for the LPLAO to operate at a specified frequency for the first clock;
- and
- a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.
A method of operating a communications apparatus, comprising:
- tracking real time based on a first clock provided by a low-power low-accuracy oscillator (LPLAO) purposely mistuned by lowering a load capacitance of the LPLAO to be less than what is required for the LPLAO to operate at a specified frequency for the first clock to provide said first clock using less power but with less accuracy than if correctly tuned for said specified frequency;
- during an operational mode, executing a communications application based on a second clock provided by a high-accuracy oscillator at a frequency that is higher than a frequency of said first clock;
- entering a sleep mode for a period of real time measured by said tracking;
- comparing said first clock to said second clock;
- and
- adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.
A communications apparatus, comprising:
- a real time unit configured for tracking real time based on a first clock;
- application circuitry that executes a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
- a high-accuracy oscillator configured to provide said second clock at a frequency that is higher than a frequency of said first clock;
- an oscillator purposely mistuned by lowering a load capacitance of the oscillator to be less than what is required for the oscillator to operate at a specified frequency for the first clock;
- and
- a calibration unit configured for comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.
A method of operating a communications apparatus, comprising:
- tracking real time based on a first dock;
- executing a communications application based on a second clock during an operational mode, said application circuitry configured to enter a sleep mode for a period of real time measured by said real time unit during said sleep mode;
- providing said second clock at a frequency that is higher than a frequency of said first clock;
- purposely mistuning an oscillator by lowering a load capacitance of the oscillator to be less than what is required for the oscillator to operate at a specified frequency for the first clock;
- and
- comparing said first clock with said second clock, and adjusting said tracking in accordance with a digital adjustment amount determined by said comparing.
Dependencies are inferred from the claim text.