Method and apparatus of frequency synthesis

A method comprising:

• receiving a first clock and a clock multiplication factor;
• modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor;
• establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor;
• deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with a noise cancellation signal and a gain control signal;
• establishing analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector;
• filtering the analog timing error signal into an oscillator control signal using a filtering circuit;
• outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator;
• outputting the second clock by dividing down the fifth clock in accordance with the division factor;
• establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero;
• and
• adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal.