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US 9,853,647 B2Granted
Transition enforcing coding receiver for sampling vector signals without using clock and data recovery
AssigneeMediatek Inc.
InventorChing-Hsiang Chang
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Abstract
A transition enforcing coding (TEC) receiver includes a first delay line circuit, a transition detection circuit, and a data sampling circuit. The first delay line circuit delays a plurality of vector signals to generate a plurality of delayed vector signals, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing determined based on an output of the transition detection circuit.
Claims20
A transition enforcing coding (TEC) receiver comprising:
- a first delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific delayed vector signal among the delayed vector signals;
- and
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on an output of the transition detection circuit;
- wherein the TEC receiver determines the sampling timing without using clock and data recovery (CDR).
2 more elements
A transition enforcing coding (TEC) receiver comprising:
- a first delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific delayed vector signal among the delayed vector signals;
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing;
- a second delay line circuit, arranged to generate a delayed signal according to an output of the transition detection circuit, wherein the sampling timing is determined based on the delayed signal;
- and
- a frequency divider, arranged to perform frequency division upon the output of the transition detection circuit to generate a clock signal to the second delay line circuit;
- wherein the second delay line circuit delays the clock signal to generate a delayed clock signal as the delayed signal, and the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the vector signals according to a rising edge of the delayed clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the vector signals according to a falling edge of the delayed clock signal, respectively.
7 more elements
A transition enforcing coding (TEC) receiver comprising:
- a first delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific delayed vector signal among the delayed vector signals;
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing;
- a second delay line circuit, arranged to generate a delayed signal according to an output of the transition detection circuit, wherein the sampling timing is determined based on the delayed signal;
- and
- a frequency divider, arranged to perform frequency division upon the delayed signal generated from delaying the output of the transition detection circuit for generating a clock signal to the data sampling circuit;
- wherein the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the vector signals according to a rising edge of the clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the vector signals according to a falling edge of the clock signal, respectively.
7 more elements
A transition enforcing coding (TEC) receiver comprising:
- a first delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific delayed vector signal among the delayed vector signals;
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on an output of the transition detection circuit;
- and
- a frequency divider, arranged to perform frequency division upon the output of the transition detection circuit to generate a clock signal to the data sampling circuit;
- wherein the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the vector signals according to a rising edge of the clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the vector signals according to a falling edge of the clock signal, respectively.
6 more elements
A transition enforcing coding (TEC) receiver comprising:
- a transition detection circuit, arranged to detect a transition of at least one specific vector signal among a plurality of vector signals;
- a delay line circuit, arranged to generate a delayed signal according to an output of the transition detection circuit;
- and
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on the delayed signal;
- wherein the TEC receiver determines the sampling timing without using clock and data recovery (CDR).
2 more elements
A transition enforcing coding (TEC) receiver comprising:
- a transition detection circuit, arranged to detect a transition of at least one specific vector signal among a plurality of vector signals;
- a delay line circuit, arranged to generate a delayed signal according to an output of the transition detection circuit;
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on the delayed signal;
- and
- a frequency divider, arranged to perform frequency division upon the output of the transition detection circuit to generate a clock signal to the delay line circuit;
- wherein the delay line circuit delays the clock signal to generate a delayed clock signal as the delayed signal;
- and the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the vector signals according to a rising edge of the delayed clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the vector signals according to a falling edge of the delayed clock signal, respectively.
7 more elements
A transition enforcing coding (TEC) receiver comprising:
- a transition detection circuit, arranged to detect a transition of at least one specific vector signal among a plurality of vector signals;
- a delay line circuit, arranged to generate a delayed signal according to an output of the transition detection circuit;
- a data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on the delayed signal;
- and
- a frequency divider, arranged to perform frequency division upon the delayed signal generated from delaying the output of the transition detection circuit for generating a clock signal to the data sampling circuit;
- wherein the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the vector signals according to a rising edge of the clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the vector signals according to a falling edge of the clock signal, respectively.
6 more elements
A transition enforcing coding (TEC) receiver comprising:
- a delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific vector signal among the vector signals;
- and
- a data sampling circuit, arranged to sample the delayed vector signals according to a sampling timing determined based on an output of the transition detection circuit;
- wherein the TEC receiver determines the sampling timing without using clock and data recovery (CDR).
2 more elements
A transition enforcing coding (TEC) receiver comprising:
- a delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;
- a transition detection circuit, arranged to detect a transition of at least one specific vector signal among the vector signals;
- a data sampling circuit, arranged to sample the delayed vector signals according to a sampling timing determined based on an output of the transition detection circuit;
- and
- a frequency divider, arranged to perform frequency division upon the output of the transition detection circuit to generate a clock signal to the data sampling circuit;
- wherein the data sampling circuit comprises:
- a plurality of first data samplers, arranged to sample the delayed vector signals according to a rising edge of the clock signal, respectively;
- and
- a plurality of second data samples, arranged to sample the delayed vector signals according to a falling edge of the clock signal, respectively.
6 more elements
Dependencies are inferred from the claim text.