Data-dependent current compensation in a voltage-mode driver

A transmitter, comprising:

• an finite impulse response (FIR) filter configured to supply a plurality of logic signals in response to input data;
• and
• a pre-driver configured to couple the plurality of logic signals to an output driver, the output driver including:
• a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node, each of the plurality of output circuits including a differential input that is coupled to receive a logic signal of the plurality of logic signals and a differential output that is coupled to a common output node;
• at least one voltage regulator coupled to a respective at least one of the first voltage supply node and the second voltage supply node;
• a current compensation circuit, including:
• a switch coupled in series with a current source, the series combination of the switch and the current source coupled between the first voltage supply node and the second voltage supply node;
• and
• an event detector coupled to the switch to supply an enable signal, the event detector configured to control state of the enable signal based on presence of a pattern in the plurality of logic signals, wherein the event detector comprises a logic gate configured to compare a first logic signal of the plurality of logic signals with a second logic signal of the plurality of logic signals to generate the enable signal.

A method of controlling an output driver in a transmitter, comprising:

• receiving a plurality of logic signals from an equalizer in the transmitter;
• coupling each of the plurality of logic signals to at least one of a plurality of output circuits of the output driver, the plurality of output circuits coupled between a first voltage supply node and a second voltage supply node, at least one of the first voltage supply node and the second voltage supply node coupled to a voltage regulator;
• detecting a pattern in the plurality of logic signals;
• and
• enabling at least one of a plurality of current sources coupled between the first voltage supply node and the second voltage supply node,
• wherein the first logic signal is generated from a current state of input data to the equalizer and the second logic signal is generated from a delayed state or an advanced state of the input data with respect to the current state, wherein the pattern of the plurality in logic signals occurs when the current state of the input data is different from at least one of the delayed state and the advanced state of the input data, and wherein the at least one current source is enabled in response to detection of the pattern and disabled in response to absence of the pattern.