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US 9,853,633 B1Granted
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry
AssigneeGSI Technology, Inc.
InventorsYu-Chi Cheng, Patrick Chuang, Jae-Hyeong Kim
Life of this patent
Estimating the term…
Abstract
Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
Claims31
A circuit, comprising
- a locked loop circuit;
- a plurality of clock tree circuits coupled to an output of the locked loop circuit, each clock tree circuit generating an output signal;
- and
- a phase averaging circuit coupled to the output of at least two of the plurality of clock tree circuits, the phase averaging circuit comprising a selection circuit that selects at least two of the plurality of clock tree circuits for the phase averaging circuit and the phase averaging circuit providing a feedback signal to the locked loop circuit, wherein a maximum skew between the output of each clock tree circuit and an input of the locked loop circuit is reduced.
1 more element
A method for reducing skew in a circuit, comprising:
- outputting a plurality of output signals from a plurality of clock tree circuits, the plurality of clock tree circuits coupled to a first circuit;
- averaging the plurality of output signals by a phase averaging circuit to generate a feedback signal, wherein averaging the plurality of output signals further comprises selecting a leading output signal from the plurality of clock tree circuits, selecting a lagging output signal from the plurality of clock tree circuits and averaging the leading output signal and the lagging output signal to generate the feedback signal;
- and
- inputting the feedback signal to the first circuit, wherein a maximum skew between the output signals from the plurality of clock tree circuits and an input of the first circuit is reduced.
1 more element
A method of operating a circuit, comprising:
- receiving an input clock signal to a first circuit;
- receiving an output of the first circuit by a plurality of clock tree circuits;
- receiving outputs of the plurality of clock tree circuits by a phase averaging circuit that averages the outputs of the plurality of clock tree circuits to generate an output, wherein averaging the plurality of output signals further comprises selecting a leading output signal from the plurality of clock tree circuits, selecting a lagging output signal from the plurality of clock tree circuits and averaging the leading output signal and the lagging output signal to generate the feedback signal;
- and
- receiving an output of the phase averaging circuit by the first circuit.
2 more elements
A semiconductor device, comprising:
- a clock circuit that controls a timing of operations within the semiconductor device;
- the clock circuit having:
- a locked loop circuit;
- a plurality of clock tree circuits coupled to an output of the locked loop circuit, each clock tree circuit generating an output signal;
- and
- a phase averaging circuit coupled to the output of at least two of the plurality of clock tree circuits, the phase averaging circuit comprising a selection circuit that selects at least two of the plurality of clock tree circuits for the phase averaging circuit and providing in a feedback signal to the locked loop circuit, wherein a maximum skew between the output of each clock tree circuit and an input of the locked loop circuit is reduced.
3 more elements
A method for reducing skew in a semiconductor circuit, comprising:
- outputting a plurality of output signals from a plurality of clock tree circuits, the plurality of clock tree circuits coupled to a first circuit;
- averaging the plurality of output signals by a phase averaging circuit to generate a feedback signal, wherein averaging the plurality of output signals further comprises selecting a leading output signal from the plurality of clock tree circuits, selecting a lagging output signal from the plurality of clock tree circuits and averaging the leading output signal and the lagging output signal to generate the feedback signal;
- and
- inputting the feedback signal to the first circuit, wherein a maximum skew between the output signals from the plurality of clock tree circuits and an input of the first circuit is reduced.
1 more element
Dependencies are inferred from the claim text.