Skew-tolerant flip-flop

A flip-flop comprising:

• a master latch configured to receive a data signal and a scan input signal;
• a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the scan input signal to the slave latch based on a scan enable signal received by the master latch;
• and
• circuitry configured to generate multiple clock signals based on an input clock signal, the clock signals including (i) a first clock signal that is provided to the master latch, and (ii) a second clock signal that is provided to the slave latch, the circuitry including:
• a first logic gate configured to (i) receive the scan enable signal, and (ii) generate an output that varies based on a logic level of the scan enable signal, and
• a second logic gate configured to generate the first or second clock signal based on the output of the first logic gate, wherein edge transitions of the first clock signal are delayed in time in comparison to edge transitions of the second clock signal when the scan enable signal has a first logic level, and wherein the first clock signal includes edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level different from the first logic level.

A method for providing clock signals to a flip-flop having a master latch and a slave latch, the method comprising:

• receiving a scan enable signal;
• receiving an input clock signal;
• generating first and second clock signals based on one or both of the input clock signal and the scan enable signal, the generating of the first and second clock signals including (i) providing the scan enable signal to a first logic gate, the first logic gate generating an output that varies based on a logic level of the scan enable signal, and (ii) using a second logic gate to generate the first or second clock signal based on the output of the first logic gate, the first clock signal not including edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a first logic level, and the first clock signal including edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level different from the first logic level;
• providing the first clock signal to the master latch;
• and
• providing the second clock signal to the slave latch.