Linearized dynamic amplifier

A differential amplifier comprising:

• a positive leg having:
• at least one positive leg transistor;
• a positive leg output capacitor coupled between the at least one positive leg transistor and ground;
• first positive leg degeneration capacitor switching circuitry;
• and
• second positive leg degeneration capacitor switching circuitry;
• a negative leg having:
• at least one negative leg transistor;
• a negative leg output capacitor coupled between the at least one negative leg transistor and ground;
• first negative leg degeneration capacitor switching circuitry;
• and
• second negative leg degeneration capacitor switching circuitry;
• a first degeneration capacitor coupled between the second positive leg degeneration capacitor switching circuitry and the first negative leg degeneration capacitor switching circuitry;
• and
• a second degeneration capacitor coupled between the first positive leg degeneration capacitor switching circuitry and the second negative leg degeneration capacitor switching circuitry;
• and
• positive leg biasing circuitry configured to bias current of the at least one positive leg transistor and negative leg biasing circuitry configured to bias the at least one negative leg transistor, the positive leg biasing circuitry and the negative leg biasing circuitry producing biasing based on capacitance of the first and second degeneration capacitors and a sampling time during an amplification period.

A method of operating a differential amplifier comprising:

• during a reset period:
• discharging a first positive leg degeneration capacitor that couples between at least one positive leg transistor and ground;
• discharging a first negative leg degeneration capacitor that couples between at least one negative leg transistor and ground;
• during an amplification period:
• enabling a first side the first positive leg degeneration capacitor to float with a source of the at least one positive leg transistor;
• enabling a first side of the first negative leg degeneration capacitor to float with a source of the at least one negative leg transistor;
• applying a positive phase differential voltage signal to a gate of the at least one positive leg transistor;
• applying a negative phase differential voltage signal to a gate of the at least one negative leg transistor;
• biasing current of the at least one positive leg transistor based on capacitance of the first positive leg degeneration capacitor and a sampling time during an amplification period;
• and
• biasing current of the at least one negative leg transistor based on capacitance of the negative leg degeneration capacitor and the sampling time during the amplification period, wherein:
• the differential amplifier is a stage amplifier of an analog to digital converter (ADC);
• and
• the amplification period is based upon a sampling clock period of the ADC.