Perfectly symmetric gate-all-around FET on suspended nanowire
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Abstract
A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
Claims9
A semiconductor device comprising:
- a plurality of suspended nanowires;
- a gate structure present on a channel region portion of the plurality of suspended nanowires, the gate structure having a uniform length extending from an upper surface of the gate structure to the base of the gate structure;
- a dielectric spacer having a graded composition in direct contact with the gate structure, the dielectric spacer being composed of single material layer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure, the graded composition defined by a decreasing oxygen or nitrogen concentration in a direction extending from an exterior surface of the dielectric spacer in a direction towards a center of the gate structure that the dielectric spacer is abutting;
- and
- source and drain regions present on source and drain region portions of the plurality of suspended nanowires.
Dependencies are inferred from the claim text.