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US 9,853,161 B2Granted
Thin film transistor with polycrystalline semiconductor formed therein
AssigneeNLT Technologies, Ltd.
InventorKunihiro Shiota
Life of this patent
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Abstract
A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.
Claims7
A thin film transistor comprising:
- a semiconductor layer formed on a substrate, said semiconductor layer comprising a polycrystalline semi-conductor;
- a gate electrode formed on said semiconductor layer with a gate insulating film interposed between said semiconductor layer and said gate electrode;
- and
- source/drain regions, doped with an impurity, formed in said semiconductor layer with said gate electrode being sandwiched between said source/drain regions,
- wherein an impurity concentration is uniformly distributed over all of said source/drain regions within a range of 2.5×1018/cm3 to 5.5×1018/cm3, all of the source and drain regions being defined as an entire region at least from each of both ends of said gate electrode to a corresponding one of a plurality of contact regions being in contact with source/drain wirings,
- wherein contact resistance values at said contact regions each are greater than 40,000Ω and less than 360,000Ω, the contact resistance values resulting from contact of said source/drain regions with said source/drain wirings, and
- wherein sheet resistance values of said source/drain regions each are greater than 1.5×105Ω/square and less than 5 ×105Ω/square.
4 more elements
An electronic device comprising:
- a thin film transistor, said thin film transistor comprising:
- a polycrystalline semiconductor layer formed on a substrate;
- a gate electrode formed on said polycrystalline semiconductor layer with a gate insulating film interposed between said polycrystalline semiconductor layer and said gate electrode;
- and
- source/drain regions, doped with an impurity, formed in said polycrystalline semiconductor layer with said gate electrode being sandwiched between said source/drain regions,
- wherein an impurity concentration is uniformly distributed over all of said source/drain regions within a range of 2.5×1018 /cm3 to 5.5×1018/cm3, all of the source and drain regions being defined as an entire region at least from each of both ends of said gate electrode to a corresponding one of a plurality of contact regions being in contact with source/drain wirings,
- wherein contact resistance values at said contact regions each are greater than 40,000Ω and less than 360,000Ω, the contact resistance values resulting from contact of said source/drain regions with said source/drain wirings, and
- wherein sheet resistance values of said source/drain regions each are greater than 1.5×105Ω/square and less than 5 ×105Ω/square.
5 more elements
Dependencies are inferred from the claim text.