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US 9,853,157 B2Granted
MOSFETs with multiple dislocation planes
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWei-Yuan Lu
Life of this patent
Estimating the term…
Abstract
A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.
Claims20
A device comprising:
- a semiconductor region having a top surface;
- a gate electrode comprising a portion over the semiconductor region;
- a source/drain region adjacent to the gate electrode;
- a first dislocation plane adjacent to the gate electrode and in the semiconductor region;
- a second dislocation plane un-parallel to the first dislocation plane, wherein both the first dislocation plane and the second dislocation plane extend into the source/drain region, and both the first dislocation plane and the second dislocation plane have lower portions increasingly closer to a middle vertical line of the gate electrode than respective upper portions;
- and
- an isolation region extending into the semiconductor region, wherein the isolation region has a first top surface and a second top surface lower than the first top surface, with the second top surface being between the first top surface and the semiconductor region, and a pitch-off line of the first dislocation plane is higher than the second top surface of the isolation region.
4 more elements
A device comprising:
- a semiconductor region;
- a gate electrode comprising a portion over the semiconductor region;
- a source/drain region on a side of the gate electrode and in the semiconductor region;
- a main spacer having an inner sidewall contacting a sidewall of the gate electrode, wherein the main spacer is substantially free from hydrogen;
- a first offset spacer having an inner sidewall contacting an outer sidewall of the main spacer, wherein the first offset spacer comprises hydrogen;
- and
- a first dislocation plane extending into the source/drain region, wherein the first dislocation plane has a first tilt angle smaller than about 45 degrees, with the first tilt angle being an angle between the first dislocation plane and a top surface of a semiconductor region.
4 more elements
A device comprising:
- a semiconductor region;
- a gate electrode comprising a portion over the semiconductor region;
- a source/drain region on a side of the gate electrode and in the semiconductor region;
- a first dislocation plane extending into the source/drain region;
- a second dislocation plane extending into the source/drain region;
- a third dislocation plane extending into the source/drain region, wherein two of the first dislocation plane, the second dislocation plane, and the third dislocation plane are un-parallel to each other;
- and
- an isolation region having a sidewall contacting a sidewall of the semiconductor region, with the isolation region having a recess, and both a sidewall of the isolation region and a sidewall of the source/drain region are exposed to the recess, and the first dislocation plane has pinch-off line higher than a bottom of the recess.
5 more elements
Dependencies are inferred from the claim text.