Embedded source or drain region of transistor with downward tapered region under facet region

A Field Effect Transistor (FET) structure, comprising:

• a body structure;
• fin spacers;
• a gate structure formed over the body structure;
• and
• a source or drain region which is embedded in the body structure beside the gate structure, and abuts and is extended beyond the body structure,
• wherein the source or drain region contains stressor material with a lattice constant different from that of the body structure;
• and
• the source or drain region comprises:
• a first region that comprises facets;
• and
• a second region that comprises downward tapered sidewalls under the first region;
• wherein the fin spacers abut the second region in between the fin spacers.

A semiconductor structure, comprising:

• a substrate;
• a fin structure formed in and extended beyond the substrate;
• dielectric structures;
• an epitaxial region embedded in the fin structure, abutting the fin structure extended beyond the substrate, and extended beyond the dielectric structure;
• wherein the epitaxial region contains stressor material with a lattice constant different from that of the fin structure;
• and
• the epitaxial region comprises:
• a first region formed above a first level at a top of the dielectric structures;
• and
• a second region that comprises downward tapered side walls;
• wherein the downward tapered side walls are formed on opposite sides of the fin structure along a width of the fin structure, formed under the first level and formed in between the dielectric structures.