Fully silicided linerless middle-of-line (MOL) contact

#The present invention relates to metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to contacts in MOSFET transistors.

#The MOSFET is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).

#The FinFET is a type of MOSFET. The FinFET is a double-gate or multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The “fin” refers to the narrow channel between source and drain regions. A thin dielectric layer on either side of the fin separates the fin channel from the gate.

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIGS. 1-9 illustrate exemplary methods of making semiconductor devices according to a first embodiment, in which:

#FIG. 1 is a cross-sectional side view of source/drain regions between gate stacks disposed over a substrate;

#As semiconductor devices scale to smaller dimensions, contact resistance may increase, which may decrease external device performance. Some methods for decreasing contact resistance include changes to contact materials. Because metal liners used in contacts may have higher resistivity than bulk metals, increasing the proportion of metal liners to bulk metals in device contact vias may increase overall device resistance. Devices that include small, i.e., 10×10 nanometer (nm) square vias, for example, are the most negatively impacted by the high resistance liners.

#Accordingly, various embodiments described herein provide devices and methods of making semiconductor devices with source/drain contacts without a metal liner. The methods form a low resistance via/contact to the source/drain region of a transistor. In some embodiments, the source/drain regions and vias are filled with, for example, amorphous silicon, a metal, or a silicon-metal alloy. A low temperature silicidation is performed to provide a low resistance via/contact without a liner on the via sidewall. A barrier layer disposed onto the contact prevents further silicidation. Like reference numerals refer to like elements across different embodiments.

#The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.