Floating grid and crown-shaping poly for improving ILD CMP dishing

An integrated circuit (IC) defined in a semiconductor substrate, the IC comprising:

• an inter-layer dielectric (ILD) layer;
• a plurality of polysilicon structures disposed within the inter-layer dielectric layer, wherein the plurality of polysilicon structures are packed with respect to one another to define a first packing density;
• one of a wide oxide diffusion (OD) region of the inter-layer dielectric layer or a wide polysilicon structure, wherein the wide oxide diffusion region or wide polysilicon structure is disposed proximate to the plurality of polysilicon structures;
• and
• a plurality of dummy structures disposed directly above the respective wide oxide diffusion region or wide polysilicon structure, wherein the plurality of dummy structures are packed with respect to one another to define a second packing density, wherein the first packing density and second packing density are substantially similar, and wherein the plurality of dummy structures define an anti-dishing structure configured to generally inhibit a dishing of a surface of the respective wide oxide diffusion region or the wide polysilicon structure concurrent with a chemical-mechanical polish of a surface of the substrate.