III-N based high power transistor with InAlGaN barrier
AssigneeFujitsu Limited
InventorAtsushi Yamada
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Abstract
A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a plurality of contact layers formed over portions of the first semiconductor layer, a second semiconductor layer formed over another portion of the first semiconductor layer and on side surfaces of the contact layers, a source electrode formed on one of the contact layers, a drain electrode formed on another one of the contact layers, and a gate electrode formed on the second semiconductor layer. The first semiconductor layer is formed of a material including GaN, the second semiconductor layer is formed of Inx1Aly1Ga1-x1-y1N (0<x1≦0.2, 0<y1<1), and the contact layers are formed of a material including GaN.
Claims11
A semiconductor device, comprising:
- a substrate;
- a first semiconductor layer formed over the substrate;
- a plurality of contact layers formed over portions of the first semiconductor layer;
- a second semiconductor layer formed over another portion of the first semiconductor layer and on lateral side surfaces of the plurality of contact layers;
- a source electrode formed on one of the plurality of contact layers;
- a drain electrode formed on another one of the plurality of contact layers;
- and
- a gate electrode formed on the second semiconductor layer, wherein
- the first semiconductor layer is formed of a material including GaN;
- the second semiconductor layer is formed of Inx1Aly1Ga1-x1-y1N (0<x1≦0.2, 0<y1<1);
- and
- the plurality of contact layers are formed of a material including GaN.
Dependencies are inferred from the claim text.