Tunnel field effect transistor (TFET) with lateral oxidation
AssigneeBoard of Regents, The University of Texas System
InventorsJack C. Lee, Han Zhao
Life of this patent
Estimating the term…
Abstract
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.
Claims22
An electrical component, comprising:
- a first layer including a source region and an oxide region, wherein the oxide region is positioned laterally relative to the source region, and wherein the oxide region is different from a gate oxide layer;
- a second layer on top of and in contact with the first layer, wherein the second layer includes a tunnel region, and wherein the tunnel region is positioned to overlay a portion of the source region and substantially an entirety of the oxide region;
- a third layer on top of a portion of the second layer, wherein the portion of the second layer is positioned at least partially on top of the oxide region, and wherein the third layer includes a channel region;
- and
- a fourth layer on top of and in contact with the third layer, wherein the fourth layer includes a drain region.
A tunnel field-effect transistor (TFET), comprising:
- a source region and an oxide region, wherein the oxide region is positioned laterally relative to the source region;
- a tunnel region on top of and in contact with the source region and the oxide region, wherein the tunnel region is positioned to overlay a portion of the source region and substantially an entirety of the oxide region;
- a passivation layer on top of and in contact with the tunnel region;
- a channel region on top of and in contact with a portion of the passivation layer, wherein the channel region is positioned at least partially on top of the oxide region;
- and
- a drain region on top of and in contact with the channel region.
A process to manufacture an electrical component, the process comprising:
- forming a first layer including a source region and an oxide region, wherein the oxide region is positioned laterally relative to the source region, and wherein the oxide region is different from a gate oxide layer;
- forming a second layer on top of and in contact with the first layer, wherein the second layer includes a tunnel region, and wherein the tunnel region is positioned to overlay a portion of the source region and substantially an entirety of the oxide region;
- forming a third layer on top of a portion of the second layer, wherein the portion of the second layer is positioned at least partially on top of the oxide region, and wherein the third layer includes a channel region;
- and
- forming a fourth layer on top of and in contact with the third layer, wherein the fourth layer includes a drain region.
A process to manufacture a tunnel field-effect transistor (TFET), the process comprising:
- forming a source region and an oxide region, wherein the oxide region is positioned laterally relative to the source region;
- forming a tunnel region on top of and in contact with the source region and the oxide region, wherein the tunnel region is positioned to overlay a portion of the source region and substantially an entirety of the oxide region;
- forming a passivation layer on top of and in contact with the tunnel region;
- forming a channel region on top of and in contact with a portion of the passivation layer, wherein the channel region is positioned at least partially on top of the oxide region;
- and
- forming a drain region on top of and in contact with the channel region.
Dependencies are inferred from the claim text.