US 9,853,128 B2Granted

Devices and methods of forming unmerged epitaxy for FinFET device

AssigneeGlobalfoundries Inc.

InventorsHui Zang, Bingwu Liu

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Abstract

Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Claims14

Dependent claims

A method comprising:

obtaining a wafer having at least one source, at least one drain, and at least one fin;
exposing at least a portion of the at least one fin;
forming at least one sacrificial gate structure;
forming a first layer of an epitaxial growth on the at least one fin, wherein the first layer of epitaxial growth comprises a first side and a second side;
and
depositing a first interlayer dielectric layer over the wafer;
planarizing the first interlayer dielectric layer;
exposing at least a portion of the first layer of an epitaxial growth, wherein exposing at least a portion of the first layer of epitaxial growth includes etching away a portion of the first layer of epitaxial growth to form a top surface of the first layer of epitaxial growth and an unexposed portion of the first side and an unexposed portion of the second side, the unexposed portions of the first and second sides contacting the first interlayer dielectric layer;
forming at least one second layer of an epitaxial growth on the first layer of an epitaxial growth, wherein the at least one second layer of epitaxial growth comprises a bottom surface, a first side surface, and a second side surface;
depositing at least one barrier layer over the at least one second layer of an epitaxial growth and the first interlayer dielectric layer, wherein the at least one barrier layer directly contacts the first side surface and the second side surface of the at least one second layer of epitaxial growth;
and
depositing at least one flowable oxide layer over the wafer, wherein the at least one flowable oxide layer directly contacts the at least one barrier layer.

9 more elements

A method comprising:

obtaining a wafer having at least one source, at least one drain, and at least one fin;
exposing at least a portion of the at least one fin;
forming at least one sacrificial gate structure;
forming a first layer of an epitaxial growth on the at least one fin, wherein the first layer of epitaxial growth comprises at least a first side and a second side;
depositing a first interlayer dielectric layer over the wafer;
planarizing the first interlayer dielectric layer;
exposing at least a portion of the first layer of an epitaxial growth, wherein exposing at least a portion of the first layer of epitaxial growth includes etching away a portion of the first layer of epitaxial growth to form a top surface of the first layer of epitaxial growth, an exposed portion of the first side, and an exposed portion of the second side, and wherein the exposed portions of the first and second sides are positioned above the first interlayer dielectric layer;
forming a second layer of an epitaxial growth on the first layer of epitaxial growth, wherein the second layer of epitaxial growth comprises at least a third side and a fourth side;
depositing a second interlayer dielectric layer over the wafer;
planarizing the second interlayer dielectric layer;
exposing at least a portion of the second layer of epitaxial growth, wherein exposing at least a portion of the second layer of epitaxial growth includes etching away a portion of the second layer of epitaxial growth to form a top surface of the second layer of epitaxial growth, an exposed portion of the third side, and an exposed portion of the fourth side, and wherein the exposed portions of the third and fourth sides of the second layer of epitaxial growth are positioned above the second interlayer dielectric layer;
forming at least one third layer of an epitaxial growth on the second layer of epitaxial growth, wherein the third layer of epitaxial growth comprises at least a fifth side and a sixth side;
and depositing at least one barrier layer over at least a portion of the at least one third layer of epitaxial growth, wherein the at least one barrier layer directly contacts the fifth side and the sixth side of the at least one third layer of epitaxial growth.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/735,283Filed 10 Jun 2015
Published: US 2016/0365451 A115 Dec 2016
Granted: 26 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…