Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

A method for fabricating a vertical field-effect-transistor, the method comprising:

• forming a structure comprising a substrate, a source/drain layer, isolation regions, and a plurality of fins disposed on and in contact with first source/drain layer;
• forming a sacrificial spacer in contact with the plurality of fins and the first source/drain layer;
• after forming the sacrificial spacer, forming silicide in a portion of the first source/drain layer and in contact with the sacrificial spacer;
• after forming the silicide, removing the sacrificial spacer;
• forming a first spacer layer in contact with at least the silicide, the first source/drain layer and the plurality of fins;
• after the sacrificial spacer has been removed, forming a gate structure in contact with the plurality of fins and the first spacer layer;
• forming a second spacer layer in contact with the gate structure and the plurality of fins;
• and
• forming a second source/drain layer in contact with second spacer layer and the plurality of fins;
• after forming the silicide and prior to forming the gate structure, removing the sacrificial spacer.