Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers

Method of making at least one transistor with at least one semiconducting nanowire, including at least:

• a) making at least one first semiconducting nanowire on a support, a first portion of the nanowire intended to form part of a transistor channel being partially covered by a dummy gate, the dummy gate and the first nanowire being surrounded by a first dielectric layer,
• b) removal of the dummy gate, forming a first free space around which first parts of the first dielectric layer are arranged,
• c) first ion implantation in at least one second part of the first dielectric layer located between the first portion of the first nanowire and the support, the first parts of the first dielectric layer protecting third parts of the first dielectric layer from this first ion implantation,
• d) selective etching of the second part of the first dielectric layer, forming a second free space,
• e) making a gate in the first and second free spaces, and a dielectric portion located on the gate and on the first parts of the first dielectric layer,
• f) second ion implantation in fourth parts of the first dielectric layer surrounding the second portions of the first nanowire intended to form part of the transistor source and drain regions, the dielectric portion protecting the first and third parts of the first dielectric layer from this second ion implantation,
• g) selective etching of the fourth parts of the first dielectric layer.