Integration of an auxiliary device with a clamping device in a transient voltage suppressor
AssigneeBourns, Inc.
InventorsAndrew J. Morrish, Tao Wei
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AssigneeBourns, Inc.
InventorsAndrew J. Morrish, Tao Wei
Estimating the term…
Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.
A method of making a transient voltage suppressor (TVS), the method comprising:
Dependencies are inferred from the claim text.