Partial sacrificial dummy gate with CMOS device with high-k metal gate

A gate structure in a semiconductor device, comprising:

• a patterned gate stack formed on a substrate;
• first spacers formed on vertical sidewalls of the gate stack;
• second spacers formed on a portion of vertical sidewalls of the first spacers, the first spacers extending above a top surface of the second spacers and having a greater height than the second spacers and a base offset from a base of the second spacers;
• source and drain regions on opposite sides and adjacent to the first spacers, and in direct contact with the base of the second spacers;
• and
• silicided regions disposed over the source and drain regions and the patterned gate stack, the first and second spacers extending above a top surface of the silicide regions positioned over the patterned gate stack.