Side bottom contact RRAM structure

An integrated circuit device, comprising:

• a plurality of lower metal interconnect lines extending in parallel with one another within a lower inter-level dielectric (ILD) layer over a substrate;
• a first plurality of bottom dielectric pads disposed over a first lower metal interconnect line and spaced apart from one another along a length of the first lower metal interconnect line;
• a first plurality of bottom electrodes disposed over the first plurality of bottom dielectric pads, respectively;
• a first plurality of RRAM dielectric structures, each having a variable resistance, disposed over the first plurality of bottom electrodes, respectively;
• a first plurality of top electrodes disposed over the plurality of RRAM dielectric structures, respectively;
• and
• a first bottom contact structure disposed over the first lower metal interconnect line and including a first plurality of ring-shaped contact structures that surround the first plurality of bottom electrodes, respectively, the first plurality of ring-shaped contact structures electrically coupling plurality of lower metal interconnect lines to outer sidewalls of the first plurality of bottom electrodes.

A method of forming an integrated circuit device,

• forming a plurality of RRAM cell stacks in rows and column over a lower metal interconnect line, the RRAM cell stacks respectively including a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance;
• forming a bottom contact structure on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode;
• and
• forming an upper metal interconnect line electrically coupled to the top electrode;
• wherein the plurality of RRAM cell stacks is formed by a process comprising:
• forming a bottom electrode layer over the lower metal interconnect line, a RRAM dielectric layer over the bottom electrode layer, and a top electrode layer over the RRAM dielectric layer;
• patterning the top electrode layer to form a top electrode;
• forming a sidewall spacer alongside the top electrode;
• and
• patterning the RRAM dielectric layer and the bottom electrode layer according to the sidewall spacer and the top electrode to form the RRAM dielectric and the bottom electrode.

An integrated circuit device, comprising:

• a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer;
• a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively comprising a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance, wherein a bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode;
• a bottom dielectric layer separating the bottom electrode and the lower metal interconnect line;
• and
• a top dielectric layer disposed over the lower metal interconnect line, continuously extending along sidewalls of the bottom contact structure, and overlying a top surface of the top electrode.