Vertical bit line non-volatile memory systems and methods of fabrication

An apparatus, comprising:

• a first global bit line and a second global bit line elongated in a first direction and separated in a second direction substantially orthogonal to the first direction;
• a first vertical thin film transistor (TFT) select device and a second vertical thin film transistor (TFT) select device overlying the first global bit line;
• a gate dielectric layer extending vertically along two vertical sidewalls of each layer stack line and horizontally over the first global bit line, wherein the gate dielectric layer includes horizontal portions extending in the first direction over the global bit lines between adjacent layer stack lines in the first direction and vertical portions extending along the vertical sidewalls of each layer stack line;
• a dielectric base elongated in the second direction over the first global bit line and the second global bit line and extending in the first direction between the first TFT select device and the second TFT select device;
• and
• a first gate separated from the first TFT select device by the gate dielectric layer;
• and
• a second gate separate from the second TFT select device by the gate dielectric layer, wherein the dielectric base extends vertically between a lower surface of the first and second gates and an upper surface of the horizontal portions of the gate dielectric layer.

An apparatus, comprising:

• a first vertical thin film transistor (TFT) select device and a second vertical thin film transistor (TFT) select device overlying a global bit line, the global bit line extending in a first horizontal direction and separated from a second global bit line in a second direction substantially orthogonal to the first horizontal direction;
• a gate dielectric layer extending vertically along two vertical sidewalls of the first TFT select device and two vertical sidewalls of the second TFT select device, the gate dielectric layer extending continuously in the first direction from a first vertical sidewall of the first TFT select device to a second vertical sidewall of the second TFT select device;
• a first gate separated from the first TFT select device by the gate dielectric layer;
• a second gate separated from the second TFT select device by the gate dielectric layer;
• a dielectric fill material insulating the first gate from the second gate in the first directions;
• and
• a dielectric base elongated in the second direction over the first global bit line and the second global bit line and extending in the first direction between the first TFT select device and the second TFT select device, wherein the dielectric base extends vertically between the first gate and the gate dielectric layer and vertically between the second gate and the gate dielectric layer.