CMOS-based thermopile with reduced thermal conductance

A method of forming an integrated circuit, the method comprising:

• providing a substrate comprising silicon-based semiconductor material;
• forming isolation trenches in the substrate, the substrate between the isolation trenches providing active areas of the integrated circuit, the active areas including active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
• forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit;
• and
• implanting germanium into the n-type thermoelectric elements and the p-type thermoelectric elements with a dose sufficient to provide at least 0.10 atomic percent germanium in the n-type thermoelectric elements and the p-type thermoelectric elements.