Memory devices having common source lines including layers of different materials
AssigneeSamsung Electronics Co., Ltd.
InventorsKwang Soo Kim, Jae Hoon Jang, Byoung Keun Son
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Abstract
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.
Claims17
A memory device, comprising:
- a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate;
- a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate;
- a source area disposed in the substrate to extend in a first direction and including impurities;
- and
- a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials, wherein the common source line comprises:
- a first layer disposed on the source area;
- and
- a second layer disposed on the first layer and being thinner than the first layer,
- wherein the second layer includes a barrier layer disposed on an upper surface of the first layer and a metal layer disposed on the barrier layer.
A memory device, comprising:
- a substrate;
- a source area disposed in the substrate to extend in a first direction and including n-type impurities;
- a plurality of channel areas extending in a direction perpendicular to an upper surface of the substrate;
- a plurality of gate electrode layers stacked on the upper surface of the substrate and disposed to be adjacent to at least a portion of the plurality of channel areas;
- and
- a common source line layer disposed on the source area to extend in the first direction, and including a first layer containing polysilicon having a higher concentration of n-type impurities than the source area and a second layer disposed on an upper surface of the first layer and containing at least one of a metal, a metal silicide, and a metal compound.
A vertical memory device comprising:
- a gate structure including a plurality of gate electrodes stacked on a substrate;
- a source area in the substrate, the source area extending in a first direction and including impurities;
- and
- a common source line extending in a direction perpendicular to an upper surface of the substrate to be connected to the source area and including a plurality of layers containing different materials, wherein the common source line comprises:
- a first layer disposed on the source area and including polysilicon doped with impurities;
- and
- a second layer disposed on the first layer and including a barrier layer on an upper surface of the first layer and a metal layer on the barrier layer, wherein the second layer is thinner than the first layer and extends longer than the first layer in the first direction.
Dependencies are inferred from the claim text.