Memory device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKi Jeong Kim, O Ik Kwon, Jong Kyoung Park, Su Jee Sunwoo
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Abstract
A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.
Claims16
A memory device, comprising:
- a plurality of gate electrode layers extending in a first direction, the gate electrode layers having different lengths on a substrate to form a step structure;
- an interlayer insulating layer on the gate electrode layers;
- a plurality of contact plugs connected to the gate electrode layers through the interlayer insulating layer;
- at least one contact insulating layer within the interlayer insulating layer and surrounding one or more of the contact plugs, the at least one contact insulating layer extending in the first direction;
- and
- a plurality of recesses in upper portions of the gate electrode layers, wherein the recesses are in a connection region outside of a cell array region and wherein each of the recesses has a shape corresponding to a shape of an outer surface of the at least one contact insulating layer.
A method of manufacturing a memory device, the method comprising:
- forming gate electrode layers extending in a first direction, the gate electrode layers having different lengths on a substrate to form a step structure;
- forming an interlayer insulating layer on the gate electrode layers;
- removing at least a portion of the interlayer insulating layer to form an opening in a connection region outside of a cell array region, the opening including first opening regions and a second opening region connecting the first opening regions to each other and exposing the gate electrode layers;
- partially filling the opening with an insulating layer to form contact holes;
- and
- filling the contact holes with a conductive material to form contact plugs.
A memory device, comprising:
- a plurality of gate electrode layers extending in a first direction, the gate electrode layers having different lengths on a substrate to form a step structure;
- an interlayer insulating layer on the gate electrode layers;
- a plurality of contact plugs connected to the gate electrode layers through the interlayer insulating layer;
- at least one contact insulating layer within the interlayer insulating layer and surrounding one or more of the contact plugs, the at least one contact insulating layer extending in the first direction;
- and
- a plurality of dummy channel columns adjacent to first ends of the gate electrode layers.
Dependencies are inferred from the claim text.