Split-gate flash cell formed on recessed substrate

A semiconductor device comprising:

• a logic transistor formed on a logic region of a substrate, the logic transistor comprising a metal-gate including a planarized surface above and substantially parallel to a first surface of the substrate in the logic region;
• and
• a non-volatile memory (NVM) cell comprising a select gate and a memory gate formed on a surface in a memory region of the substrate, wherein the memory region of the substrate is recessed to a first depth relative to the substrate in the logic region, and top surfaces of the select gate and memory gate are below an elevation of the planarized surface of the metal-gate,
• wherein at least one of the top surfaces of the select gate and memory gate comprise a silicide.

A semiconductor device comprising:

• a logic transistor formed on a logic region of a substrate, the logic transistor comprising a metal-gate including a planarized surface above and substantially parallel to a first surface of the substrate in the logic region;
• and
• a non-volatile memory (NVM) cell comprising a select gate and a memory gate formed in a memory region of the substrate, the memory gate formed in a first recess in the memory region recessed to a first depth relative to the first surface of the substrate in the logic region, and the select gate formed in a second recess in first recess recessed to a second depth relative to the first surface that is greater than the first depth,
• wherein top surfaces of the select gate and memory gate comprise a silicide and are below an elevation of the planarized surface of the metal-gate above the first surface of the substrate.