Layout scheme and method for forming device cells in semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
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Abstract
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
Claims18
A method for forming a semiconductor word line decoder device, comprising:
- forming a plurality of word line decoder device cells, each word line decoder device cell including multiple patterned metal-metal interconnect layers;
- forming a first pair of transistors in a first word line decoder device cell of the plurality of word line decoder device cells and having respective gates coupled by a first polysilicon lead and further coupled by a metal lead disposed in one of the multiple patterned metal-metal interconnect layers;
- forming a second pair of transistors in a second word line decoder device cell of the plurality of word line decoder device cells and having respective further gates coupled by a second polysilicon lead and the metal lead, wherein the metal lead is coupled with both the first polysilicon lead and the second polysilicon lead.
A method, comprising:
- forming a plurality of first cells, each of the first cells including at least a first transistor having a first poly gate electrode formed over a first active area;
- forming a plurality of second cells, each of the second cells including at least a second transistor having a second poly gate electrode formed over a second active area, each of the second poly gate electrodes coupled to a respective one of the first poly gate electrodes by a first poly lead, thereby forming a plurality of the first poly leads;
- and
- forming a first conductive lead in a first interconnect layer, the first conductive lead coupled to the plurality of the first poly leads, the first poly gate electrodes, and to the second poly gate electrodes.
A method, comprising:
- forming a plurality of first poly gate electrodes of first transistors over a first active area;
- forming a plurality of second poly gate electrodes of second transistors over a second active area, each of the plurality of the second poly gate electrodes disposed at a first distance from a respective one of the plurality of the first poly gate electrodes;
- connecting each of the plurality of the first poly gate electrodes to a respective one of the plurality of the second poly gate electrodes with a first poly lead, thereby forming a plurality of the first poly leads;
- and
- forming a first conductive lead in a first interconnect layer, the first conductive lead coupled to the plurality of the first poly leads and to the first poly gate electrodes and to the second poly gate electrodes.
Dependencies are inferred from the claim text.