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US 9,853,033 B2Granted
Memory device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells. At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around configurations and a plurality of active blocks. A portion of one of the active blocks serves as a source or a drain of one of the transistors. The active blocks in any adjacent two of the memory cells are isolated from each other.
Claims20
A memory device comprising:
- an array of memory cells, at least one of the memory cells comprising:
- a plurality of transistors with vertical-gate-all-around configurations;
- a plurality of active blocks, a portion of one of the active blocks serving as a source or a drain of one of the transistors, wherein the active blocks in any adjacent two of the memory cells are isolated from each other;
- a first gate plate serving as a gate of a first transistor of the plurality of the transistors;
- and
- a storage node coupled to first and second active blocks of the plurality of the active blocks and having a top surface flush with a top surface of the first gate plate.
3 more elements
A memory device comprising:
- an array of memory cells including upper and lower memory cells, at least one of the memory cells comprising:
- a plurality of transistors with vertical-gate-all-around configurations;
- and
- a plurality of active blocks, a portion of one of the active blocks serving as a source or a drain of one of the transistors, wherein the active blocks in one of the memory cells are distant from a boundary of the one of the memory cells;
- and
- a plurality of gate plates serving as gates of the transistors and including first and second gate plates, wherein a first gap between the first and second gate plates of the upper memory cell is longer than a second gap between the first gate plate of the upper memory cell and the first gate plate of the lower memory cell.
3 more elements
A method for manufacturing a memory device, comprising:
- forming an array of memory cells on or above a substrate, wherein forming at least one of the memory cells comprises:
- forming a plurality of active blocks on or above the substrate, and the active blocks in any adjacent two of the memory cells are isolated from each other;
- forming a plurality of transistors with vertical-gate-all-around configurations on or above the substrate, wherein a portion of at least one of the active blocks serves as a first source/drain region of one of the transistors;
- forming a storage node that interconnects two of the active blocks;
- and
- forming a second source/drain region above the first source/drain region after forming the storage node.
3 more elements
Dependencies are inferred from the claim text.