Fin field effect transistor

A semiconductor device, comprising:

• a semiconductor substrate having an NMOS region and a PMOS region;
• a first fin on the PMOS region of the semiconductor substrate and a second fin on the NMOS region of the semiconductor substrate;
• a first dielectric layer on the semiconductor substrate, a surface of the first dielectric layer being lower than a top surface of both of the first fin and the second fin;
• a gate structure on the first dielectric layer and covering across the first fin and the second fin, the first fin being substantially entirely covered by the gate structure;
• a first semiconductor layer on the PMOS region of the semiconductor substrate at each side of the gate structure and in contact with the first fin, wherein the first fin is underneath the gate structure, the first dielectric layer being located at both sides of each of the first semiconductor layer and the second fin;
• a second semiconductor layer on a top surface of a portion of the second fin exposed at the each side of the gate structure;
• a second dielectric layer on the first dielectric layer and substantially filling space between the first semiconductor layer, the first dielectric layer, and the second fin, the second dielectric layer covering the first semiconductor layer;
• and
• the second semicondutor layer at least on a surface of the second fin and above the second dielectric layer.