Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit

A display device comprising:

• a first transistor in a pixel portion over a substrate;
• a power supply line over the substrate;
• a protection circuit electrically connected to the power supply line, the protection circuit comprising a second transistor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer over the substrate, a gate insulating film over the oxide semiconductor layer and a gate electrode over the gate insulating film, the oxide semiconductor layer comprising a source region, a drain region and a channel formation region between the source region and the drain region;
• a pixel electrode electrically connected to one of the source region and the drain region of the first transistor;
• and
• an insulating film covering at least side surfaces of the gate electrode of the first transistor, the insulating film comprising aluminum oxide wherein the insulating film is in contact with side surfaces of the gate insulating film of the first transistor and an upper surface of the oxide semiconductor layer of the first transistor,
• wherein the source region and the drain region have a lower resistance than the channel formation region, and
• wherein the gate electrode of the second transistor is electrically connected to one of the source region and the drain region of the second transistor.

A semiconductor device comprising:

• an oxide semiconductor layer over a substrate;
• a gate insulating film over the oxide semiconductor layer;
• a gate electrode over the gate insulating film with the gate insulating film therebetween, the oxide semiconductor layer comprising a source region, a drain region and a channel formation region between the source region and the drain region;
• an insulating film covering at least side surfaces of the gate electrode, the insulating film comprising aluminum oxide,
• wherein the insulating film is in contact with side surfaces of the gate insulating film and an upper surface of the oxide semiconductor layer,
• wherein the source region and the drain region have a lower resistance than the channel formation region.