Connecting techniques for stacked CMOS devices

An integrated circuit (IC), comprising:

• a first device tier comprising a first semiconductor substrate;
• an inter-tier interconnecting structure disposed within the first semiconductor substrate and comprising a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure, wherein the inter-tier interconnecting structure comprises one or more conductive layers extending between the first and second connection points and wherein the first connection point and the second connection point are not vertically aligned;
• and
• a second device tier electrically coupled to the first device tier by the inter-tier interconnecting structure.

An integrated circuit (IC), comprising:

• a first device tier comprising a first semiconductor substrate;
• a first inter-tier interconnecting structure arranged inside the first semiconductor substrate, wherein the first inter-tier interconnecting structure comprises a first conductive layer and a second conductive layer with different patterns;
• and
• a second device tier electrically connected to the first device tier by the first inter-tier interconnecting structure.