Semiconductor device and method of manufacturing the same

#Embodiments described herein relate to a semiconductor device and a method of manufacturing the same.

#Due to size shrinkage of a semiconductor device, there are problems that reduction of cross sections of interconnects causes an increase in resistance of the interconnects and reduction of a distance between the interconnects causes an increase in capacitance between the interconnects. Therefore, it is considered that the interconnects are formed of copper (Cu) that has a low specific resistance to reduce the resistance of the interconnects. Furthermore, it is considered that air gaps are formed between the interconnects to reduce the capacitance between the interconnects.

#Examples of the interconnects in the semiconductor device include a RIE (reactive ion etching) interconnect that is formed by RIE and a damascene interconnect that is formed by a damascene process. However, since copper cannot be processed by RIE, copper cannot be used for the RIE interconnect and therefore the resistance of the RIE interconnect cannot be reduced by copper. In contrast, copper can be used for the damascene interconnect. However, when an interconnect trench for embedding the damascene interconnect is minute, the interconnect thickness is limited due to the embedding limit of copper. Therefore, when the damascene interconnect is formed of copper, the interconnect thickness cannot be large enough and therefore the resistance of the damascene interconnect cannot be sufficiently reduced.

#FIGS. 1A to 1C are cross sectional views showing a structure of a semiconductor device of a first embodiment;

#FIGS. 2A to 7B are cross sectional views showing a method of manufacturing the semiconductor device of the first embodiment;

#FIGS. 8A to 8C are cross sectional views showing a structure of a semiconductor device of a second embodiment;

#Embodiments will now be explained with reference to the accompanying drawings.

#In one embodiment, a semiconductor device includes a substrate. The device further includes a first interconnect which includes a first layer provided on the substrate and formed of a first interconnect material, and a second layer provided on the first layer, formed of a second interconnect material different from the first interconnect material, and having a first lower face, and has a first width. The device further includes a second interconnect which includes a third layer provided on the substrate and formed of the first interconnect material, a fourth layer provided on the third layer, formed of the second interconnect material, and having a second lower face lower than the first lower face, and has a second width greater than the first width.

#FIGS. 1A to 1C are cross sectional views showing a structure of a semiconductor device of a first embodiment. An example of the semiconductor device of the present embodiment is a semiconductor memory such as a NAND flash memory.