Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit

A method comprising:

• providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon;
• patterning an array of mandrels into the mandrel layer such that the array of mandrels includes:
• a plurality of minimum width mandrels having a minimum width and a minimum mandrel pitch, and
• a wide mandrel section having a width and a length that are at least equal to two minimum mandrel pitches;
• patterning a plurality of mandrel openings into the array of mandrels, the mandrel openings having at least a minimum opening width and having a minimum opening length required to provide a minimum mandrel continuity cut through a mandrel metal line having a minimum metal line width;
• patterning a transition region opening into the array of mandrels, the transition region opening having a width and a length that are at least equal to two minimum mandrel pitches, the transition region opening being disposed between, and adjacent to, the wide mandrel section and at least two minimum width mandrels;
• forming mandrel spacers self-aligned on sidewalls of the mandrels;
• disposing and planarizing a gapfill layer over the semiconductor structure;
• forming non-mandrel pillars over the planarized gapfill layer;
• etching exposed portions of the gapfill layer to form non-mandrel plugs preserved by the pillars;
• removing the pillars to form a pattern, the pattern including the non-mandrel plugs;
• and
• utilizing the pattern to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack, the array including non-mandrel dielectric structures formed from the non-mandrel plugs.