Interconnect structure having substractive etch feature and damascene feature

#The present invention relates to methods for fabricating metal wiring layers of a semiconductor device, and more specifically, to methods of fabricating interconnect structures for semiconductor devices with minimized resistance and improved time dependent dielectric breakdown (TDDB) performance.

#An integrated circuit (IC) device may be formed with millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC device to be functional, multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect structures) or wiring formed by subtractive etch, are fabricated using BEOL (back end of line) techniques to connect the circuit elements distributed on the surface of the device. BEOL technologies must be continuously optimized through changes in process flows and material used in order to build high performance structures as critical dimensions decrease. For example, etching of small profiles using thin masking layers becomes increasingly problematic with regard to etch profile control (controlling shape of hole or trench being formed) or control of etching damage and residues. Maximizing metal volume for a given space is difficult with current technologies.

#According to one embodiment, a method of forming an interconnect structure includes depositing a first conductive material on a substrate. The method also includes subtractively etching the conductive material to form a patterned first conductive layer. The method also includes depositing a dielectric layer on the interconnect structure. The method also includes depositing a second conductive material on the dielectric layer. The method also includes removing the second conductive material through the top of the second metal liner.

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1A depicts a cross sectional side view of an exemplary device with idealized interconnect structures defining metal wiring.

#FIG. 1B depicts a cross sectional side view of another exemplary device with idealized interconnect structures defining metal wiring.

#The invention relates to issues pertaining to interconnect scaling in BEOL techniques. It is desirable to increase the efficiency of metal placement in wiring. Interconnect structures in BEOL technologies can be formed by damascene processes and etching. In some cases an opening in the interconnect level may be a via, extending perpendicular to the surface of IC completely through the interlayer dielectric (ILD) for connecting an overlying wire of a higher wiring level or of the present wiring level to an underlying wire of a lower wiring level. A filled via is typically simply referred to as a via or as a plug when connecting to an underlying first metallization (M1) or to an element of an underlying MOS (metal oxide semiconductor) structure.

#It is desirable to maximize the metal volume of metal wires for a given space between metal features. Conventional techniques, such as conventional damascene processes and subtractive etch processes, have resulted in inefficient use of volume in interconnect structures because of the sidewall taper angle that results from such processing. A conventional “damascene process,” forms conductors in-laid in the dielectric layer. In the context of integrated circuits, damascene means formation of a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.

#In an exemplary dual damascene process, a dielectric cap and insulator layer are deposited atop a preceding level having metal wiring. The insulator layer may have a dielectric constant k<3.0, such as SiCOH, SiON, TEOS, or silicon oxynitride. Photolithography can be used to define a via and trench pattern to be transferred into the insulator layer and dielectric cap film. Reactive ion etch (RIE) can be used to transfer the photolithography pattern to the dielectric films. Trench and via formation can involve multiple photolithography steps. Hydrofluoric acid can be used to clean the device and a metallization process can be used to deposit a barrier metal, such as tantalum nitride (TaN/Ta), cobalt (Co) and ruthenium (Ru), and seed layer, such as copper (Cu), copper manganese (CuMn), copper aluminum (CuAl), and alloys thereof. Copper reflow or electroless plating with an over burden can be used to fill and planarize the interconnect structure. An anneal can be performed to crystallize the metal. The structure can be polished by chemical mechanical polish to remove the metal overburden and repeated as desired.