Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips

A method for fabricating an electronic system comprising:

• providing a semiconductor wafer having embedded electronic bodies, the wafer surface having conductive contact pads of the electronic bodies;
• laminating an insulating first polymeric film across the wafer surface;
• providing a sheet of capacitive elements, one sheet side formed as a metal foil in touch with metal particles, surfaces of the metal particles covered with a dielectric skin, and the opposite sheet side formed by a conductive polymeric material between the metal particles, the sheet operable as a capacitor having the metal as first terminal, the conductive polymer as second terminal, and the dielectric skin of the metal particles as insulator;
• attaching the sheet by its metal foil onto the first polymeric film;
• opening sets of via-holes of a first diameter into the sheet, the first set holes reaching the metal foil, and the second set holes reaching the wafer contact pads;
• laminating an insulating second polymeric film across the wafer, filling the via-holes of the first diameter and planarizing the sheet surface;
• opening sets of through-polymer vias of a second diameter into the second polymeric film, the second diameter being smaller than the first diameter, the third set holes, nested inside the first set holes, reaching the metal foil, the fourth set holes, nested inside the second set holes, reaching a contact pad, and a fifth set holes reaching the conductive polymeric surface;
• depositing a metal seed layer onto sidewalls and bottoms of the through-polymer vias and the surface of the second polymeric film, creating redistribution traces and attachment pads on the surface;
• and
• plating metal onto the patterned seed layer to fill the through-polymer vias.