US 9,852,976 B2 · Semiconductor package and fabricating method thereof

Abstract

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Drawings

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Drawings

Claims20

Dependent claims

A semiconductor device comprising:

a first redistribution structure comprising:
a first dielectric layer comprising a first dielectric material;
a first conductive trace embedded in the first dielectric layer and comprising:
a first trace top side that is partially covered by the first dielectric layer;
a first trace bottom side that is exposed at a bottom side of the first dielectric layer;
and
a first trace lateral side that is covered by the first dielectric layer;
a first conductive via embedded in the first dielectric layer and comprising:
a first via top side that is exposed at a top side of the first dielectric layer;
a first via bottom side that is directly coupled to the first trace top side;
and
a first via lateral side that is covered by the first dielectric layer;
and
a die interconnection structure, at least a portion of which is formed on top of the first conductive via, where the die interconnection structure extends above the first dielectric layer;
a second redistribution structure on a bottom side of the first redistribution structure and comprising:
a second dielectric layer comprising a second dielectric material;
a second conductive trace;
and
a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace;
a semiconductor die attached to a top side of the first redistribution structure, where the semiconductor die comprises a conductive bump that is attached to the die interconnection structure of the first redistribution structure;
and
a mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die.

19 more elements

Dependencies are inferred from the claim text.

Description21,534 words

Summary75 words

#[Not Applicable]

Brief description of the drawings16 figures

#The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate examples of the present disclosure and, together with the description, serve to explain various principles of the present disclosure. In the drawings:

#FIGS. 1A-1J show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure.

#FIG. 2 is a flow diagram of an example method of making a semiconductor package, in accordance with various aspects of the present disclosure.

Detailed description20,964 words

#Various aspects of this disclosure provide a semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

#The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like.

#As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.”

Facts

Application

15/400,041Filed 6 Jan 2017 · continuation

Priority

11 Aug 2015

Published

US 2017/0133310 A111 May 2017

Granted

26 Dec 2017

Term ends

11 Aug 2035

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification25 codes

H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 70/099
Package substrates; Interposers; Redistribution layers [RDL]: connecting interconnections to insulating or insulated package substrates,…

Timeline

11 Aug 2015Priority claimedParent application 14/823,689
6 Jan 2017Application filedUS 15/400,041
6 Jan 2017Assigned to Amkor Technology, Inc.assignment of assignor's interest
11 May 2017PublishedUS 2017/0133310 A1
26 Dec 2017GrantedUS 9,852,976 B2
1 Aug 2018Assigned to Bank of America, N.A., AS Agentsecurity interest
12 Oct 2020Assigned to Amkor Technology Singapore Holding Pte.Ltd.assignment of assignor's interest
12 Oct 2026TodayWithin its term
11 Aug 2035Term endsEstimated

Semiconductor package and fabricating method thereof

Life of this patent

Semiconductor package and fabricating method thereof

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description21,534 words

Drawings

Classification25 codes

Life of this patent

Description21,534 words