Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices

A system comprising:

• a first semiconductor structure having plurality of gate array structures in a silicided region wherein the plurality of gate array structures are separated from each other by a first distance from each other;
• unsilicided S/D areas extending beyond the silicided region, and contacted along a periphery of the first semiconductor structure, the unsilicided S/D region including a plurality of resistors wherein a potential difference is applied in the silicided region of the first semiconductor structure and currents running between the plurality of gate array structures of the first semiconductor structure are measured and resistance on the plurality of resistors of the first semiconductor structure is determined;
• a second semiconductor structure having plurality of gate array structures in a silicided region wherein the plurality of gate array structures are separated from each other by a second distance;
• unsilicided S/D areas extending beyond the silicided region, and contacted along a periphery of the second semiconductor structure, the unsilicided S/D region including a plurality of resistors wherein the potential difference is applied in the silicided region of the second semiconductor structure and currents running between the plurality of gate array structures of the second semiconductor structure are measured and resistance on the plurality of resistors of the second semiconductor structure is determined;
• and
• at least one computer configured:
• to perform a linear-regression fit of measured resistance on the plurality of resistors in the first semiconductor structure and the plurality of resistors in the second semiconductor structure versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures in the first semiconductor structure and the second semiconductor structure based on a semiconductor device model.

A computer program product comprising program code stored on a computer-readable storage medium, which when executed by at least one computing structure, enables the at least one computing device to implement a method of determining a lateral dopant profile in a semiconductor structure by performing actions including:

• receiving currents running between a plurality of gate array structures from a first semiconductor structure with the plurality of gate array structures in a silicided region, wherein the first semiconductor structure includes unsilicided S/D regions extending beyond the silicided region, the unsilicided S/D regions including a plurality of resistors, wherein the plurality of gate array structures are separated from each other by a first distance wherein a potential difference is applied in the silicided region of the first semiconductor structure;
• determining resistance on the plurality of resistors of the first semiconductor structure;
• receiving currents running between a plurality of gate array structures from a second semiconductor structure with a plurality of gate array structures in a silicided region, wherein the second semiconductor structure includes unsilicided S/D regions extending beyond the silicided region, the unsilicided S/D regions including a plurality of resistors, wherein the plurality of gate array structures are separated from each other by a second distance wherein the potential difference is applied in the silicided region of the second semiconductor structure;
• determining resistance on the plurality of resistors of the second semiconductor structure;
• and
• performing a linear-regression fit of measured resistance on the plurality of resistors in the first semiconductor structure and the plurality of resistors in the second semiconductor structure versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures in the first semiconductor structure and the second semiconductor structure based on a semiconductor device model.