Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

A method, comprising:

• forming an N-active region and a P-active region in a semiconductor substrate;
• performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
• forming a first masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
• with said first masking layer in position, forming a first layer of a first semiconductor material on said recessed surface of said P-active region and forming a layer of a second semiconductor material on said first layer of said first semiconductor material, wherein said first semiconductor material is a different semiconductor material from said second semiconductor material;
• removing said first masking layer;
• after forming said layer of said second semiconductor material on said first layer of said first semiconductor material and removing said first masking layer, forming a second masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
• with said second masking layer in position, forming a layer of silicon-carbon on said recessed surface of said N-active region and forming a second layer of said first semiconductor material on said layer of silicon-carbon;
• removing said second masking layer;
• forming an N-type transistor in and above said N-active region;
• and
• forming a P-type transistor in and above said P-active region.

A method, comprising:

• forming an N-active region and a P-active region in a semiconductor substrate;
• performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
• forming a first masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
• with said first masking layer in position, forming a layer of silicon-carbon on said recessed surface of said N-active region and forming a first layer of a first semiconductor material on said layer of silicon-carbon;
• removing said first masking layer;
• after forming said first layer of said first semiconductor material on said layer of silicon-carbon and removing said first masking layer, forming a second masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
• with said second masking layer in position, forming a second layer of said first semiconductor material on said recessed surface of said P-active region and forming a layer of a second semiconductor material on said second layer of said first semiconductor material, wherein said first semiconductor material is a different semiconductor material from said second semiconductor material;
• removing said second masking layer;
• forming an N-type transistor in and above said N-active region;
• and
• forming a P-type transistor in and above said P-active region.