Minimizing shorting between FinFET epitaxial regions

A method comprising:

• forming a dummy gate layer on a first set of fins and a second set of fins;
• forming an opening in the dummy gate layer between the first set of fins and the second set of fins, the opening exposing an upper surface of a substrate;
• forming a dielectric region in the opening, wherein an upper surface of the dielectric region is substantially flush with an upper surface of the dummy gate layer;
• forming a dummy gate aligned with the dielectric region by patterning the dummy gate layer, the dummy gate covers a middle portion of the first set of fins and a middle portion of the second set of fins;
• replacing the dummy gate with a metal gate.

A method comprising:

• forming a dummy gate layer on a first fin group and a second fin group;
• forming an opening in the dummy gate layer between the first fin group and the second fin group, the opening exposing an upper surface of a substrate;
• forming a dielectric region in the opening, wherein an upper surface of the dielectric region is substantially flush with an upper surface of the dummy gate layer;
• forming a first dummy gate and a second dummy gate by patterning the dummy gate layer, the first dummy gate covers a middle portion of the first fin group and the second dummy gate covers a middle portion of the second fin group, and the dielectric region separates the first dummy gate from the second dummy gate;
• replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively.