Back to results
US 9,852,950 B2Granted
Superimposed transistors with auto-aligned active zone of the upper transistor
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsClaire Fenouillet-Beranger, Philippe Coronel
Life of this patent
Estimating the term…
Abstract
Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.
Claims18
A method for manufacturing an integrated circuit equipped with at least two levels of superimposed transistors, comprising:
- the creation of a plurality of plugs including at least one first plug, a second plug and a third plug on a drain region, a gate and a source region respectively of a first transistor of a first level of transistor(s), the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor and being arranged such that the first plug is spaced apart from the third plug by a distance of at least d2, the second plug is spaced apart from the first plug and from the third plug by a distance of at least d1, where d1 and d2 are planned such that d1>d2,
- forming a sacrificial support layer of thickness equal to h on the insulating later,
- forming, on the sacrificial support layer, a semi-conducting layer capable of receiving at least one channel region of a second transistor of a second level of transistor(s), where the semi-conducting layer is arranged at an end of the plugs at a height h measured between an upper face of the insulating layer covering the first transistor and a lower face of the semi-conducting layer such that h>d1,
- removing the sacrificial layer so as to form a cavity of height h formed between the semi-conducting layer and the insulating layer,
- forming a protective block in a first region of a cavity made between the insulating layer and the semi-conducting layer, where the first region is located facing the first transistor between the first plug and the third plug, the formation of the protective block comprising steps of conforming deposition of a sacrificial material in the cavity, then partial removal of the sacrificial material by isotropic etching in such a way as to preserve a block of sacrificial material between the first plug and the third plug at the end of the isotropic etching, where an active zone of the second transistor is intended to be defined facing the first plug the third plug and the protective block,
- wherein the protective block is formed furthermore of a gate dielectric layer deposited before the sacrificial material and in which the formation of the protective block comprises furthermore, after deposition of the sacrificial material and isotropic etching of the sacrificial material, the partial removal of the gate dielectric layer in the cavity, where the dielectric layer is preserved in the first region, the method furthermore comprising after definition of the active zone, steps for:
- removing the sacrificial material in the first region then,
- formation of a gate material in the cavity by conforming deposition in the cavity,
- partial removal of the gate material in the cavity by isotropic etching so as to preserve the gate material in the first region.
6 more elements
A method for manufacturing an integrated circuit equipped with at least two levels of superimposed transistors, comprising:
- forming a first transistor of a first level of transistor(s) and covering said first transistor by an insulating layer,
- forming a sacrificial support layer of thickness equal to h situated on said insulating layer,
- forming a plurality of plugs including at least one first plug, a second plug and a third plug on a drain region, a gate and a source region respectively of a first transistor of a first level of transistor(s), the first plug, the second plug and the third plug passing through said sacrificial support and said insulating layer, said plugs being arranged such that the first plug is spaced apart from the third plug by a distance of at least d2, the second plug is spaced apart from the first plug and from the third plug by a distance of at least d1, where dl and d2 are planned such that d1>d2,
- forming, on said sacrificial support layer, a semi-conducting layer capable of receiving at least one channel region of a second transistor of a second level of transistor(s), where the semi-conducting layer is arranged at an end of the plugs at a height h measured between an upper face of the insulating layer covering the first transistor and a lower face of the semi-conducting layer such that h>d1,
- removing the sacrificial layer so as to form a cavity of height h formed between the semi-conducting layer and the insulating layer,
- forming a protective block in a first region of said cavity formed between the insulating layer and the semi-conducting layer, wherein the first region is located facing the first transistor between the first plug and the third plug, the foimation of the protective block comprising steps of conforming deposition of a sacrificial material in the cavity, then partial removal of the sacrificial material by isotropic etching in such a way as to preserve a block of sacrificial material between the first plug and the third plug at the end of the isotropic etching, where an active zone of the second transistor is intended to be defined facing the first plug the third plug and the protective block,
- replacing said protective block by a transistor gate for the second transistor.
4 more elements
A method for manufacturing an integrated circuit equipped with at least two levels of superimposed transistors, comprising steps consisting of:
- creating a plurality of plugs including at least one first plug, a second plug and a third plug on a drain region, a gate and a source region respectively of a first transistor of a first level of transistor(s), the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor and passing through a sacrificial support layer of thickness equal to h on the insulating later,
- said plugs being arranged such that the first plug is spaced apart from the third plug by a distance of at least d2, the second plug is spaced apart from the first plug and from the third plug by a distance of at least d1, where d1 and d2 are planned such that d1>d2, wherein amongst the first plug, the second plug, and the third plug, at least one given plug comprises a lower conducting portion and at least an upper portion, said lower portion passing through said insulating layer and being connected to the first transistor, said upper portion being based on an insulating material and configured so as to create insulation between the lower portion and the second transistor, said upper portion passing through said sacrificial support layer
- forming, on the sacrificial support layer, a semi-conducting layer capable of receiving at least one channel region of a second transistor of a second level of transistor(s), where the semi-conducting layer is arranged at an end of the upper portion of the plugs at a height h measured between an upper face of the insulating layer covering the first transistor and a lower face of the semi-conducting layer such that h>d1,
- removing the sacrificial layer so as to fonn a cavity of height h formed between the semi-conducting layer and the insulating layer,
- forming a protective block in a first region of a cavity made between the insulating layer and the semi-conducting layer, where the first layer is located facing the first transistor between the first plug and the third plug, the formation of the protective block comprising steps of conforming deposition of a sacrificial material in the cavity, then partial removal of the sacrificial material by isotropic etching in such a way as to preserve a block of sacrificial material between the first plug and the third plug at the end of the isotropic etching, where an active zone of the second transistor is intended to be defined facing the first plug the third plug and the protective block.
2 more elements
Dependencies are inferred from the claim text.