US 9,852,945 B2Granted

Method of manufacturing a semiconductor device having a cell field portion and a contact area

AssigneeInfineon Technologies Austria AG

InventorsAndreas Meiser, Till Schloesser, Martin Poelzl

Life of this patent

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Abstract

A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.

Claims4

Dependent claims

A method of manufacturing a semiconductor device at least partially in a semiconductor substrate, the semiconductor substrate comprising a first and a second main surface, the first and the second main surfaces being opposed to each other, the method comprising forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion comprising at least a transistor comprising a gate electrode, wherein the contact area is formed by:

forming a connection substrate portion insulated from other substrate portions and comprising a part of the semiconductor substrate;
forming isolation trenches extending from the first main surface to the second main surface, wherein the connection substrate portion is insulated from other substrate portions by the isolation trenches;
and
forming an electrode adjacent to the second main surface and in contact with the connection substrate portion,
the method further comprising electrically coupling the gate electrode of the transistor of the cell field portion to the electrode adjacent to the second main surface in the contact area via the connection substrate portion.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/962,573Filed 8 Dec 2015 · division
Priority: 31 Oct 2012
Published: US 2016/0093529 A131 Mar 2016
Granted: 26 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures

Family

Application13/664,792Parent of this division · filed 31 Oct 2012
US 2016/0093529 A1Pre-grant publication · published 31 Mar 2016
US 9,231,100 B2Parent of this division
US 2014/0117438 A1Published application
US 9,852,945 B2This patent

From the US filing history. Foreign family members aren’t listed.