Backside contact to a final substrate

#Devices fabricated using semiconductor-on-insulator (SOI) technologies may exhibit certain performance improvements in comparison with comparable devices built directly in a bulk silicon substrate. Generally, an SOI wafer includes a thin device layer of semiconductor material, a handle substrate, and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the device layer from the handle substrate. Integrated circuits are fabricated using the semiconductor material of the device layer.

#Wafer thinning has been driven by the need to make packages thinner to accommodate stacking and high density packaging of chips. An SOI wafer may be thinned by removing the handle wafer from its construction. Once thinned, the backside surface of the SOI wafer may be subjected to additional operations. To lend mechanical support during thinning and the additional operations performed subsequent to thinning, the frontside surface bearing the integrated circuits may be adhesively bonded to a temporary substrate. After the additional operations are performed, a final substrate may be attached to the backside surface and the temporary substrate may be removed.

#Improved device structures and fabrication methods are needed for a backside contact to a final substrate.

#The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments and, together with a general description given above and the detailed description of the embodiments given below, serve to explain the embodiments.

#FIGS. 1-3 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an embodiment.

#FIGS. 4-5 are cross-sectional views of a portion of a substrate at successive fabrication stages of a processing method for fabricating a device structure in accordance with an alternative embodiment.

#With reference to FIG. 1 and in accordance with an embodiment, an assembly 10 includes a semiconductor-on-insulator (SOI) substrate 12 and a temporary substrate 14 that is removably attached to the SOI substrate 12. The SOI substrate 12 may include a device layer 16, a buried insulator layer 18, and a handle wafer 20. The device layer 16 is separated from the handle wafer 20 by the intervening buried insulator layer 18 and is considerably thinner than the handle wafer 20. The device layer 16 is in direct contact with a front surface 18a of the buried insulator layer 18, and the buried insulator layer 18 includes a backside or back surface 18b in direct contact with the handle wafer 20. The buried insulator layer 18 may be comprised of an electrical insulator and, in particular, may be a buried oxide layer comprised of silicon dioxide (e.g., SiO2).

#Shallow trench isolation regions 22 may be formed in the device layer 16 of the SOI substrate 12 to define a device region in the device layer 16. The shallow trench isolation regions 22 may be formed by depositing a hardmask, patterning the hardmask and device layer 16 with lithography and etching processes to define trenches, depositing an electrical insulator to fill the trenches, planarizing the electrical insulator relative to the hardmask using a chemical mechanical polishing (CMP) process, and removing the hardmask. In one embodiment, the shallow trench isolation regions 22 may be comprised of silicon dioxide (SiO2) deposited by low-pressure chemical vapor phase deposition (LPCVD), and may penetrate completely through the device layer 16 to the front surface 18a of the buried insulator layer 18.

#A trench 24 is formed that extends from a top surface 16a of the device layer 16 through the device layer 16, beyond a front surface 18a of the buried insulator layer 18 forming an interface with the device layer 16, and partially through the buried insulator layer