Solderable contact and passivation for semiconductor dies

#This invention relates to semiconductor devices and processes for their manufacture and more specifically relates to a novel solderable contact structure for semiconductor die.

#Solderable contacts for semiconductor devices are well known. Such contact structures are commonly silver-containing alloys deposited on aluminum die electrodes, which are insulated from other surfaces by an insulation passivation coating which overlaps the edges of the contact area.

#It has been found that the silver ions from the top metal layer will migrate under the passivation layer and form dendrites under prolonged exposure to electric fields and moisture. Thus, over time, the dendrites will form conductive bridges between device electrodes and device terminations, thus reducing device reliability.

#FIG. 1 is a bottom view of a Direct FET® type package of the type shown in aforementioned U.S. Pat. No. 6,624,522.

#FIG. 2 is a cross-section of the circled portion of FIG. 1, showing the area of overlap of a passivation layer and solderable metal of the prior art.

#FIG. 3 is a cross-section like that of 2, but illustrating the novel invention in which the edge of the solderable metal is spaced from the confronting edge of the epoxy passivation.

#Referring first to FIGS. 1 and 2 there is shown a bottom view of a Direct FET® type package 10 in which a MOSFET semiconductor die 11 is contained within a metal can 12 which has an open bottom, shown in Figure, and a top web 13, shown in FIGS. 2 and 3. The web 13 is connected to flanges 14 and 15 which form a contact for drain electrode 16 on the bottom surface of die 11.

#The top surface of die 11 is exposed by the open bottom of conductive can 12 and contains a source electrode having solderable contacts 20 and 21 and a solderable gate contact 22. The top surfaces of contacts 20, 21 and 22 are generally coplanar with drain contacts 14, 15 although there could be an upset of up to about 50 μm due to tolerance variations. Thus, the device is solderable at its contacts 14, 15, 20, 21 and 22 to respective corresponding contact areas on a flat circuit board (not shown). The contacts 20, 21 and 22 are insulated from one another and from the conventional termination enclosing the upper surface of die 11 by an insulation passivation layer 30.

#It is to be noted that the invention is illustrated as applied to a Direct FET® type device. However, the die 11 may be any semiconductor die which has a solderable contact which is insulated by a surrounding passivation coating.