Methods for integrated circuit design and fabrication

#The semiconductor integrated circuit industry has experienced rapid growth over the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased.

#Semiconductor fabrication relies heavily on the process of photolithography, in which light of a given frequency is used to transfer a desired pattern onto a wafer undergoing semiconductor processing. To transfer the pattern onto the wafer, a photomask is used. The photomask permits and prevents light in a desired layout onto a layer of the wafer, such as a photoresist (PR) mask, which chemically reacts to the light exposure to remove some portions of the PR mask and leaving other portions. The remaining PR mask is then used to pattern an underlying layer, which sometimes is used to pattern another underlying layer. As feature sizes have decreased, the wavelength of light used in photolithography to pattern mask layers has decreased as well, creating additional difficulties and necessitating technological advances such as the use of EUV as a light source, phase-shifting masks, and other advances.

#In some instances, multiple masks may be used to form the features of a single desired layout. Each of the multiple masks is used to create different features contained within the desired layout. However, using multiple masks to achieve a single layout can be problematic. If two adjacent features, each from a different submask, are formed too close to each other unwanted electrical connections may be formed or desired connections may not be formed. Some processes, such as self-aligned double patterning (SADP) attempt to remedy such problems, but attempts to do so by introducing a number of constraints.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H present fragmentary views of a semiconductor wafer during a fabrication process according to one or more embodiments of the present disclosure.

#FIGS. 2A, 2B, 2C, 2D, 2E, and 2F present fragmentary views of a semiconductor wafer during an additional fabrication process according to one or more embodiments of the present disclosure.

#These figures are better understood by reference to the Detail Description included below.

#The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples for simplicity and clarity. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process as well as embodiments in which additional processes may be performed between the first and second processes. Accordingly, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Many of the figures referred to herein are fragmentary in nature, showing only a portion of a substrate in which other processes may be performed and other structures and devices formed.

#Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.