Semiconductor memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorHo-Jun Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a normal memory block including a plurality of normal memory cells, a redundant memory block including a plurality of redundant memory cells used to replace defective cells among the normal memory cells, a normal buffer block configured to sense and amplify data stored in the normal memory block, a redundant buffer block configured to sense and amplify data stored in the redundant memory block, a normal latch block configured to fetch data from the normal buffer block and store the data based on a normal control signal, and a redundant latch block configured to selectively fetch data from the redundant buffer block and store the data based on a redundant control signal.
Claims19
A semiconductor memory device comprising:
- a normal memory block including a plurality of normal memory cells;
- a redundant memory block including a plurality of redundant memory cells, the plurality of redundant memory cells configured to replace defective cells among the normal memory cells;
- a normal buffer block configured to sense and amplify normal data stored in the normal memory block;
- a redundant buffer block configured to sense and amplify redundant data stored in the redundant memory block, the redundant buffer block including a plurality of redundant buffers;
- a normal latch block configured to fetch the normal data from the normal buffer block and store the normal data based on a normal control signal;
- and
- a redundant latch block including a plurality of redundant latches each configured to selectively fetch the redundant data from a respective one of the plurality of redundant buffers and store the redundant data based on whether a redundant control signal designates that respective ones of the plurality of redundant latches are active redundant latches, the active redundant latches being ones of the plurality of redundant latches corresponding to bit lines connected to repair cells.
A memory system comprising:
- a plurality of semiconductor memory devices;
- and
- a memory controller configured to control the semiconductor memory devices, wherein each of the semiconductor memory devices includes,
- a memory cell array including a plurality of normal memory cells and a plurality of redundant memory cells, each of the plurality of redundant memory cells configured to replace a defective cell among the normal memory cells,
- a sense amplifier configured to sense and amplify data stored in the memory cell array, the sense amplifier including a plurality of redundant buffers configured to sense and amplify data stored in the redundant memory cells,
- a latch block configured to fetch and store data from the sense amplifier based on a normal control signal and a redundant control signal, the latch block including a plurality of redundant latches configured to selectively fetch redundant data from a respective one of the plurality of redundant buffers and store the redundant data based on whether the redundant control signal designates that respective ones of the plurality of redundant latches are active redundant latches, the active redundant latches being one of the plurality of redundant latches corresponding to bit lines connected to repair cells,
- a control circuit configured to generate the normal control signal and the redundant control signal, and
- a one time programmable (OTP) memory configured to store a repair signal.
A semiconductor memory device, comprising:
- a latch block including a plurality of normal latches and a plurality of redundant latches, the plurality of redundant latches configured to selectively fetch redundant data from repair cells included in redundant memory cells based on a redundant control signal;
- and
- a controller configured to selectively provide the redundant control signal to ones of the plurality of redundant latches based on a repair signal, the repair signal indicating which of the plurality of redundant latches are connected to the repair cells such that the controller is configured to selectively disable ones of the plurality of redundant latches not associated with the repair cells.
Dependencies are inferred from the claim text.