US 9,852,812 B2 · Storage apparatus, memory controller, control method for storage apparatus, and program

Abstract

There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.

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Drawings

Claims6

Dependent claims

A storage apparatus, comprising:

an address obtaining section configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing has failed;
and
a write processing section configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address has failed, wherein
the address obtaining section obtains the normal write address and the alternative write address from a write command asking for the data writing, and
the write processing section performs the data writing in accordance with the write command, the address obtaining section refers to identification information to determine whether the alternative write addresses are all done with the data writing, the identification information is information for identifying which of the alternative write addresses is done with the data writing, and the address obtaining section supplies a plurality of different alternative write addresses when determining that the alternative write addresses are all done with the data writing.

2 more elements

A storage system, comprising:

an access control section configured to issue an instruction for data writing;
an address supply section configured to supply a normal write address and an alternative write address before the data writing to the normal write address, the normal write address being designated as a destination for the data writing, the alternative write address being used when the data writing has failed;
an address obtaining section configured to obtain the normal write address and the alternative write address before the data writing to the normal write address;
and
a write processing section configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address has failed, wherein
the address supply section supplies a plurality of alternative write addresses before the data writing to the normal write address,
the write processing section notifies the address supply section of identification information every time performing the data writing to any of the alternative write addresses, the identification information being information for identifying which of the alternative write addresses is done with the data writing, and
the address supply section refers to the identification information to determine whether the alternative write addresses are all done with the data writing, and when determining that the alternative write addresses are all done with the data writing, supplies a plurality of different alternative write addresses.

5 more elements

Dependencies are inferred from the claim text.

Description9,979 words

Summary1,621 words

#This application claims the benefit of Japanese Priority Patent Application JP 2013-260813 filed Dec. 18, 2013, the entire contents of which are incorporated herein by reference.

#The present disclosure relates to a storage apparatus, a memory controller, a control method for the storage apparatus, and a program run for a computer to perform the method. More specifically, the present disclosure relates to a storage apparatus performing data writing, a memory controller, a control method for the storage apparatus, and a program run for a computer to perform the method.

#In a previous storage apparatus exemplified by a memory, writing of write data is followed by verification to determine whether the data writing is successful. Herein, the verification is a process performed by the storage apparatus after the writing of write data at a write address. This verification process is to verify the write data stored in advance in the storage apparatus against data read from the write address. When there is no match between these data, a write error is notified to a memory controller.

Brief description of the drawings20 figures

#FIG. 1 is a general view of a memory system in a first embodiment of the present disclosure, showing an exemplary configuration thereof;

#FIG. 2 is a block diagram showing an exemplary configuration of a memory controller in the first embodiment;

#FIG. 3 is a block diagram showing an exemplary function structure of the memory controller in the first embodiment;

Detailed description8,003 words

#Hereinafter, embodiments of the present disclosure (hereinafter, simply referred to as embodiments) will be described with reference to the drawings. The description is given in the following order.

#1. First Embodiment (example of obtaining an alternative write address before data writing)

#2. Second Embodiment (example of obtaining a plurality of alternative write addresses before data writing)

Facts

Application

14/534,579Filed 6 Nov 2014

Priority

JP 2013-26081318 Dec 2013

Published

US 2015/0170763 A118 Jun 2015

Granted

26 Dec 2017

Term ends

19 Apr 2035

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 164 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification3 codes

G11C 29/76
Masking faults in memories by using spares or by reconfiguring: using address translation or modifications
G11C 8/06
Arrangements for selecting an address in a digital store: address interface arrangements, e.g. address buffers
G11C
Static stores

Timeline

18 Dec 2013Priority claimedJP 2013-260813
6 Nov 2014Application filedUS 14/534,579
6 Nov 2014Assigned to Sony Corporationassignment of assignor's interest
18 Jun 2015PublishedUS 2015/0170763 A1
26 Dec 2017GrantedUS 9,852,812 B2
12 Oct 2026TodayWithin its term
19 Apr 2035Term endsEstimated, includes 164 days of adjustment

Storage apparatus, memory controller, control method for storage apparatus, and program

Life of this patent

Storage apparatus, memory controller, control method for storage apparatus, and program

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description9,979 words

Drawings

Classification3 codes

Life of this patent

Description9,979 words